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[VHDL-FPGA-Verilog] VHDL

Description: 介绍Verilog HDL, 内容包括：Verilog应用，Verilog语言的构成元素，结构级描述及仿真 ，行为级描述及仿真，延时的特点及说明 介绍Verilog testbench，激励和控制和描述 结果的产生及验证，任务task及函数function 用户定义的基本单元(primitive)，可综合的Verilog描述风格等-Introduction Verilog HDL, including: Verilog applications, Verilog language of the elements, structure, level description and simulation, behavioral-level description and simulation, delay characteristics and note describes Verilog testbench, described the results of incentive and control and the generation and verification, the task task and function of the basic unit of user-defined function (primitive), can be integrated Verilog description of style
Platform: | Size: 1521664 | Author: shirley | Hits:

[VHDL-FPGA-Verilog] LIP1732CORE_system_mbus_arbiter

Description: System Verilog M bus arbiter module
Platform: | Size: 26624 | Author: jc | Hits:

[VHDL-FPGA-Verilog] uart2bus_latest.tar

Description: 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
Platform: | Size: 224256 | Author: robin | Hits:

[VHDL-FPGA-Verilog] 8051vlog

Description: 8051IP核，verilog源代码，包含测试向量，-8051 IP Core verilog code， with testbench
Platform: | Size: 251904 | Author: zhangq | Hits:

[VHDL-FPGA-Verilog] SpiMaster

Description: This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate
Platform: | Size: 9216 | Author: RutaliMulye | Hits:

[VHDL-FPGA-Verilog] mp3decoder

Description: verilog实现mp3解码程序，包括testbench-mp3 decoder verilog implementation procedures, including the testbench
Platform: | Size: 6647808 | Author: zhongduo | Hits:

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] TestBench_Primer

Description: 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-Writing testbench
Platform: | Size: 58368 | Author: xy | Hits:

[VHDL-FPGA-Verilog] small-programs-using-verilog

Description: 148个用verilog编写的小程序，易于初学者学习，部分代码还有testbench-148 small programs written using verilog, easy for beginners to learn, there are some code testbench
Platform: | Size: 37888 | Author: 宋利川 | Hits:

[VHDL-FPGA-Verilog] I2C_Verilog_Model

Description: 该源程序包是I2C的Verilog语言模型，包括以下4个部分：RTL源代码，测试平台，软件仿真代码，说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
Platform: | Size: 364544 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] SD_Controller_Verilog

Description: 该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。-This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help document.
Platform: | Size: 1659904 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] testbench

Description: 介绍如何编写verilog的仿真程序，很适合初学者-How to write verilog simulation program, it is suitable for beginners
Platform: | Size: 22528 | Author: 王阳 | Hits:

[VHDL-FPGA-Verilog] mppt_mod

Description: maximum power point tracking system (MPPT) VHDL code with testbench
Platform: | Size: 2951168 | Author: veerender | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 这是一个uart串口实现16550的实现，代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
Platform: | Size: 35840 | Author: wangli | Hits:

[VHDL-FPGA-Verilog] Viterbi_Verilog

Description: viterbi译码的verilog实现,提供相应的原程序代码和testbench -viterbi decoder verilog implementation
Platform: | Size: 3756032 | Author: ren | Hits:

[VHDL-FPGA-Verilog] ssram-and-tesebench

Description: 实现一个256x8的同步静态存储器SSRAM，用硬件描述语言Verilog写的，同时谢了测试程序-it realized a 256x8 SSRAM,writen by Hardware description language Verilog ,and include the testbench.
Platform: | Size: 1024 | Author: 李柏祥 | Hits:

[VHDL-FPGA-Verilog] verilog--maopao-paixu

Description: 用verilog实现的冒泡排序法 ，有testbench-Implemented using verilog bubble sort, there is testbench
Platform: | Size: 2048 | Author: 阿神 | Hits:

[VHDL-FPGA-Verilog] Writing-Testbenches-using-System-Verilog

Description: writing testbench in system verilog
Platform: | Size: 2764800 | Author: dk | Hits:

[VHDL-FPGA-Verilog] how-to-write-testbench

Description: 怎样写testbench ， 仿真， modelsim， system verilog or verilog， 代码风格，行为级代码-how write testbench，do simulation, modelsim, system verilog or verilog , behaveral level code
Platform: | Size: 4096 | Author: james | Hits:

[VHDL-FPGA-Verilog] how-to-write-testbench

Description: 如何写好testbench,针对verilog语言-how to write testbench，aimed to verilog
Platform: | Size: 251904 | Author: 郭良谦 | Hits:
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